VSD - Clock Tree Synthesis - Part 1
VLSI - Building a chip is like building a city!!
CTS Quality Checks (Skew, Power, Latency, etc.)
H-Tree
Quality Check of H-Tree
Clock Tree Buffering
Buffered H-Tree
H-Tree with uneven spread of Flops
Advanced H-Tree for Million Flops
Power Aware CTS (clock gating)
Static Timing Analysis with Clock Tree
Clock Tree Networks are Pillars and Columns of a Chip.
With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.
The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.
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