This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.
Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.
0
74 Ratings
Free
per course
Incentives
Shareable Certificate
100% online
Flexible deadlines
Intermediate Level
Approx. 30 hours to complete
English
Also check at
FAQs About "Hardware Description Languages for FPGA Design"
Is the online course "Hardware Description Languages for FPGA Design" free?
Yes, "Hardware Description Languages for FPGA Design" is a free online course offered on the online classes platform Coursera
About
Elektev is on a mission to organize educational content on the Internet and make it easily accessible. Elektev provides users with online course details, reviews and prices on courses aggregated from multiple online education providers. DISCLOSURE: This page may contain affiliate links, meaning when you click the links and make a purchase, we receive a commission.