FPGA Drive IIC EEPROM

This course will focus on how one FPGA communicates with one IIC EEPROM. It will finish one task: write one data into one EEPROM through one FPGA, and then read it out. After that, the system will compare the two data. If the read data and write data are the same, the system will blink one led on the FPGA board. It means both the write EEPROM function and read EEPROM function have run successfully. This course will include the key knowledge as the following:

(1) IIC basic knowledge: this course present how to calculate and generate the IIC clock, how to output the IIC start bit, data bits and the stop bit sequentially.

(2) IIC simulation skill: the sda bus of the IIC is bi-direction. This course present how to accept data the send back ACK bit and data bit through the bi-direction data bus.

(3) EEPROM IIC byte write protocol analysis and simulation;

(4) EEPROM IIC byte read protocol analysis and simulation;

(5) FPGA drive EEPROM system block, state machine analysis and coding;

(6) System debug skill: the course leave one bug in the one place, and then present how to local and fix it through the simulation wave form.

(7) This course also demo how to create and compile one Quartus project, and present how to download the bin file into FPGA board through the USB blaster degbugger.